The present invention relates to reducing latency, and more specifically, to reducing latency in Ethernet applications, such as 100G Ethernet. The Ethernet physical layer is developed according to the Open Systems Interconnection (OSI) model. Several layers are defined in the various Ethernet standards, including the Physical Layer (PHY). The Ethernet Physical Coding Sublayer (PCS) is part of the Ethernet PHY layer and performs autonegotiation, coding, and other functions.
Latency is a critical parameter in many networking applications, such as financial applications. Typical Ethernet implementations follow the IEEE functional definition. The definition by the IEEE of Forward Error Correction (FEC) function for 100G Ethernet is specified generically, independent of the PCS function. The standard FEC implementation follows the classical Layered Functional Model, with a FEC sublayer situated between the PCS and Physical Medium Attachment (PMA) sublayer. The effective latency therefore is the sum of PCS latency and FEC latency. A significant part of the FEC latency is due to functions that are symmetrical with PCS functions.